Project descriptionWe are looking for a Verification Engineer to work on IP-level using a UVM-based environment. The role involves writing the test cases in UVM, performing functional Verification with RTL, and debugging issu...

Project descriptionWe are looking for a Verification Engineer to work on IP-level using a UVM-based environment. The role involves writing the test cases in UVM, performing functional Verification with RTL, and debugging issu...

Project descriptionWe are seeking an experienced Functional Verification Engineer with strong expertise in System Verilog/UVM to develop and maintain verification environments for block-level and IP-level designs. The ideal c...